Semiconductor device

ABSTRACT

A method for fabricating a semiconductor device is described. A stacked gate dielectric is formed over a substrate, including a first dielectric layer, a second dielectric layer and a third dielectric layer from bottom to top. A conductive layer is formed on the stacked gate dielectric and then patterned to form a gate conductor. The exposed portion of the third and the second dielectric layers are removed with a selective wet cleaning step. S/D extension regions are formed in the substrate with the gate conductor as a mask. A first spacer is formed on the sidewall of the gate conductor and a portion of the first dielectric layer exposed by the first spacer is removed. S/D regions are formed in the substrate at both sides of the first spacer. A metal silicide layer is formed on the S/D regions.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a Divisional of and claims priority benefit ofpatent application Ser. No. 13/403,591, filed on Feb. 23, 2012, nowallowed. The entirety of the abovementioned patent application is herebyincorporated by reference herein and made a part of specification.

BACKGROUND OF THE INVENTION

1. Field of Invention

This invention relates to a semiconductor device, and a method forfabricating a semiconductor device.

2. Description of Related Art

Trapping-type memory devices, which include a charge-trapping layerinstead of a floating gate between the substrate and the control gate,have been widely applied in the related fields.

In a conventional fabrication process of the trapping-type memory, thecontrol gates are defined after the corresponding conductive layer isdeposited over the charge-trapping layer, source/drain (S/D) regions areformed in the substrate after a spacer is formed on the sidewall of eachcontrol gate, and the trapping layer is not patterned between the stepof defining the control gates and the step of forming the spacer.

Because the charge-trapping layer is not patterned before the spacerdefining the bounds of the S/D regions is formed, metal silicide cannotbe formed on the S/D regions. Hence, the sheet resistance of the S/Dregions is high so that the device speed is lowered. Furthermore, thecontact resistance of the S/D regions is high even open.

SUMMARY OF THE INVENTION

Accordingly, this invention provides a method for fabricating asemiconductor device, which can be utilized to solve the above issues inthe prior art.

This invention also provides a semiconductor device that is fabricatedby the method of this invention.

The method for fabricating a semiconductor device of this invention isdescribed below. A stacked gate dielectric is formed over a substrate,including a first dielectric layer, a second dielectric layer and athird dielectric layer from bottom to top. A conductive layer is formedon the stacked gate dielectric. The conductive layer is patterned toform a gate conductor. The exposed portion of the third dielectric layeris removed with the gate conductor as a mask. The exposed portion of thesecond dielectric layer is removed with the gate conductor as a mask.S/D extension regions are formed in the substrate with the gateconductor as a mask. A first spacer is formed on the sidewall of thegate conductor and the portion of the first dielectric layer exposed bythe first spacer is removed. S/D regions are formed in the substrate atboth sides of the first spacer. A metal silicide layer is formed atleast on the S/D regions.

In an embodiment, the above method further comprises, after the firstspacer is formed but before the S/D regions are formed, forming a secondspacer on the sidewall of the first spacer, wherein the S/D regions areformed in the substrate outside of the sidewall of the second spacer. Inanother embodiment, the S/D regions are formed in the substrate outsideof the sidewall of the first spacer.

The semiconductor device of this invention includes a gate conductor ona substrate, a stacked gate dielectric between the gate conductor andthe substrate, a first spacer on the sidewall of the gate conductor, S/Dextension regions in the substrate outside of the sidewall of the gateconductor, S/D regions in the substrate outside of the sidewall of thefirst spacer, and a metal silicide layer at least on the S/D regions.The stacked gate dielectric includes, from bottom to top, a firstdielectric layer, a second dielectric layer and a third dielectriclayer, wherein the sidewall of the second dielectric layer is alignedwith that of the gate conductor.

In an embodiment, the semiconductor device further includes a secondspacer between the gate conductor and first spacer, wherein the sidewallof the first dielectric layer is aligned with that of the second spacer.In another embodiment, the sidewall of the first dielectric layer isaligned with that of the first spacer.

Because the portion of the second dielectric layer exposed by the gateconductor and the portion of the first dielectric layer exposed by thefirst spacer are removed in this invention, the metal salicide layer canbe formed on the S/D regions to reduce the electrical resistance,especially when the method is applied to the fabrication of anon-volatile memory device with the second dielectric layer being a(SiN) charge-trapping layer and the first dielectric layer being atunnel layer.

In order to make the aforementioned and other objects, features andadvantages of the present invention comprehensible, a preferredembodiment accompanied with figures is described in detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1D illustrate, in a cross-sectional view, a method forfabricating a semiconductor device according to a first embodiment ofthis invention, wherein FIG. 1D also illustrates the semiconductordevice according to the first embodiment.

FIGS. 2A and 2B illustrate, in a cross-sectional view, a latter half ofa method for fabricating a semiconductor device according to a secondembodiment of this invention, wherein the former half of the method isillustrated in FIGS. 1A and 1B, and FIG. 2B also illustrates thesemiconductor device according to the second embodiment.

DESCRIPTION OF EMBODIMENTS

It is noted that the following embodiments are intended to furtherexplain this invention but not to limit its scope. For example, thoughthe first dielectric layer, the second dielectric layer and the thirddielectric layer in the stacked gate dielectric are respectively atunnel layer, a charge-trapping layer and a top insulator of anon-volatile memory cell, they can be films of a different device thathave other functions.

FIGS. 1A-1D illustrate, in a cross-sectional view, a method forfabricating a semiconductor device according to a first embodiment ofthis invention, wherein FIG. 1D also illustrates the semiconductordevice according to the first embodiment.

Referring to FIG. 1A, a semiconductor substrate 100 is provided, havingthereon a logic area 102 and a memory array area 104. In the logic area102, a gate dielectric layer 106 is formed on the substrate 100. In thememory array area 104, a stacked gate dielectric including a tunnellayer 108, a charge-trapping layer 110 and a top insulator 112 frombottom to top is formed on the substrate 100. A conductive layer forforming gate electrodes is then deposited and patterned to form gateconductors 114 a of the logic transistors in the logic area 102 and gateconductors 114 b of the memory cell transistors in the memory array area104.

The substrate 100 may include lightly doped single-crystal or epitaxialsilicon. The gate dielectric layer 106 may include SiO₂ or SiON. Thetunnel layer 108 may include silicon oxide, and may have a thickness of10-50 angstroms. The charge-trapping layer 110 may include siliconnitride (SiN), and may have a thickness of 20-150 angstroms. The topinsulator 112 may include silicon oxide, and may have a thickness of10-50 angstroms. The gate conductors 114 a and 114 b may include dopedpoly-Si. When the tunnel layer 108 includes silicon oxide, thecharge-trapping layer 110 includes SiN, the top insulator 112 includessilicon oxide and the gate conductor 114 b includes doped poly-Si, thesemiconductor substrate 100, the tunnel layer 108, the charge-trappinglayer 110, the top insulator 112 and a gate conductor 114 b togetherconstitute a semiconductor-oxide-nitride-oxide-silicon (SONOS) structureof a memory cell.

Referring to FIG. 1B, the exposed portion of the gate dielectric layer106 in the logic area 102 and the exposed portion of the top insulator112 in the memory array area 104 are removed with the gate conductor 114a and 114 b as a mask, possibly through a cleaning process that usuallyuses HF_((aq)). The exposed portion of the charge-trapping layer 110 inthe memory array area 104 is then selectively removed with a wet cleanstep with HF/H₂SO₄, so that the sidewall of the remainingcharge-trapping layer 110 is aligned with that of the gate conductor 114b. S/D extension regions 116 are then formed in the substrate 100 in thelogic area 102 and the memory array area 104, possibly through an ionimplantation process, with the gate conductors 114 a and 114 b as amask.

It is noted that a re-oxidation process may be performed to the gateconductors 114 a and 114 b after the exposed portion of thecharge-trapping layer 110 is removed but before the S/D extensionregions 116 are formed, mainly for repairing the damages on the gateconductors 114 a and 114 b. If such a re-oxidation process is performed,a thin SiO₂ film will be formed on the sidewall and the top of each ofthe gate conductors 114 a and 114 b.

Referring to FIG. 1C, a first spacer 120 a and a first spacer 120 b arerespectively formed on the sidewalls of the gate conductors 114 a and114 b in the logic area 102 and the memory array area 104, and theportion of the tunnel layer 108 exposed by the first spacer 120 b in thememory array area 104 is removed. The first spacers 120 a and 120 b mayinclude silicon oxide or SiN, and may each have a width of 50-200angstroms. The first spacers 120 a and 120 b may be formed by depositinga substantially conformal layer of its material and anisotropicallyetching the same, and the portion of the tunnel layer 108 exposed by thefirst spacer 120 b in the memory array area 104 may be removed bycontinuing the anisotropic etching.

Referring to FIG. 1D, a second spacer 124 a and a second spacer 124 bare formed on the sidewall of the first spacer 120 a in the logic area102 and the sidewall of the first spacer 120 b in the memory array area104, respectively, possibly in a similar way of forming the firstspacers 120 a and 120 b. The second spacers 124 a and 124 b may includeSiN or SiO₂, and may each have a width of 50-750 angstroms.

Thereafter, S/D regions 128 are formed in the substrate 100 outside ofthe sidewall of each of the second spacers 124 a and 124 b in the logicarea 102 and the memory array area 104, respectively. A metal silicidelayer 132 is then formed on all the S/D regions 128 and the gateconductors 114 a and 114 b, possibly through a salicide (self-alignedsilicide) process that typically includes depositing a refractory metallayer, reacting the metal with silicon and then removing the unreactedmetal.

In the above first embodiment, because the portion of thecharge-trapping layer 110 exposed by the gate conductors 114 b and theportion of the tunnel layer 108 exposed by the first spacer 120 b areremoved in the memory array area 104, the metal salicide layer 132 canbe formed on the S/D regions 128 in the memory array area 104 to reducethe electrical resistance of the memory cells.

Besides, although two spacers 120 a/b and 124 a/b are formed on thesidewall of each gate conductor 114 a/b in the above embodiment with thefirst spacer 120 b defining the bounds of the tunnel layer 108 in thememory array area 104 and the second spacer 124 a/b defining the boundsof the S/D regions 128, there may alternatively be only one spacer onthe sidewall of each gate conductor defining the bound of the tunnellayer 108 in the memory array area 104 and also defining the bounds ofthe S/D regions 128 in other embodiments, such as the following secondembodiment of this invention.

FIGS. 2A and 2B illustrate, in a cross-sectional view, a latter half ofa method for fabricating a semiconductor device according to the 2^(nd)embodiment of this invention, wherein the former half of the method isillustrated in FIGS. 1A and 1B, and FIG. 2B also illustrates thesemiconductor device according to the second embodiment.

Referring to FIG. 2A, after the structure as illustrated in FIG. 1B isobtained, a spacer 140 a and a spacer 140 b are respectively formed onthe sidewalls of the gate conductors 114 a and 114 b in the logic area102 and the memory array area 104, and the portion of the tunnel layer108 exposed by the spacer 140 b in the memory array area 104 is removed.The spacers 140 a and 140 b may include silicon oxide or SiN, and mayeach have a width of 50-750 angstroms. It is possible to form thespacers 140 a and 140 b and remove the portion of the tunnel layer 108exposed by the spacer 140 b in a similar way as in the aforementionedprocess of forming the spacers 120 a and 120 b and removing the exposedtunnel layer 108.

Referring to FIG. 2B, S/D regions 128 are then formed in the substrate100 outside of the sidewall of each of the spacers 140 a and 140 b inthe logic area 102 and the memory array area 104, respectively. A metalsilicide layer 132 is then formed on all the S/D regions 128 and thegate conductors 114 a and 114 b, possibly in the same way as mentionedabove.

In the above second embodiment, because the portion of thecharge-trapping layer 110 exposed by the gate conductors 114 b and theportion of the tunnel layer 108 exposed by the spacer 140 b are removedin the memory array area 104, the metal salicide layer 132 can be formedon the S/D regions 128 in the memory array area 104 to reduce theelectrical resistance of the memory cells.

This invention has been disclosed above in the preferred embodiments,but is not limited to those. It is known to persons skilled in the artthat some modifications and innovations may be made without departingfrom the spirit and scope of this invention. Hence, the scope of thisinvention should be defined by the following claims.

What is claimed is:
 1. A semiconductor device, comprising: a gateconductor on a substrate; a stacked gate dielectric between the gateconductor and the substrate, comprising, from bottom to top, a firstdielectric layer, a second dielectric layer and a third dielectriclayer, wherein a sidewall of the second dielectric layer is aligned witha sidewall of the gate conductor; a first spacer on the sidewall of thegate conductor; source/drain (S/D) extension regions in the substrateoutside of the sidewall of the gate conductor; S/D regions in thesubstrate outside of a sidewall of the first spacer; and a metalsilicide layer at least on the S/D regions.
 2. The semiconductor deviceof claim 1, further comprising a second spacer between the gateconductor and first spacer, wherein a sidewall of the first dielectriclayer is aligned with a sidewall of the second spacer.
 3. Thesemiconductor device of claim 1, wherein a sidewall of the firstdielectric layer is aligned with the sidewall of the first spacer. 4.The semiconductor device of claim 1, wherein the second dielectric layercomprises a charge-trapping layer.
 5. The semiconductor device of claim4, wherein the charge-trapping layer comprises silicon nitride.
 6. Thesemiconductor device of claim 5, which comprises a memory cell, whereinthe gate conductor comprises dopes polysilicon, the first and the thirddielectric layers comprise silicon oxide, and the substrate, the firstdielectric layer, the second dielectric layer, the third dielectriclayer and the gate conductor constitute asemiconductor-oxide-nitride-oxide-silicon (SONOS) structure of thememory cell.
 7. The semiconductor device of claim 1, wherein the gateconductor comprises doped polysilicon, and the metal silicide layer isalso on the gate conductor.